Low-Power and Area-Efficient Carry Select Adder


Downloads per month over past year

BSSV RAMESH BABU, . and UDAY KUMAR, M. and Venugopal, K.R. and BABJI, B. (2016) Low-Power and Area-Efficient Carry Select Adder. International Journal of VLSI System Design and Communication Systems, 4 (4). 0252-0255. ISSN 2322-0929


Download (391kB) | Preview


Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA. Based on this modification 8-, 16-, 32-, and 64-b square-root CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA architecture. The proposed design has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the delay. This work evaluates the performance of the proposed designs in terms of delay, area, power, and their products by hand with logical effort and through custom design and layout in CMOS process technology. The results analysis shows that the proposed CSLA structure takes only 30.385 ns which is better than the regular SQRT CSLA.

Item Type: Article
Uncontrolled Keywords: Application-Specific Integrated Circuit(ASIC), Area-Efficient, CSLA, Low Powe
Subjects: Faculty of Engineering > Computer Science & Information Science Engineering
Divisions: University Visvesvarayya College of Engineering > Department of Computer Science and Information Science Engineering
Depositing User: Ms. Shwetha A C
Date Deposited: 12 Oct 2021 11:02
Last Modified: 12 Oct 2021 11:02
URI: http://eprints-bangaloreuniversity.in/id/eprint/10120

Actions (login required)

View Item View Item